The invention relates to a memory device, including a non-volatile memory device, a method for operating a memory device, and an apparatus for use with a memory device.
In the case of conventional memory devices, including conventional semiconductor memory devices, one differentiates between so-called functional memory devices (e.g. PLAs, PALs, etc.), and so-called table memory devices, e.g. ROM devices (ROM=Read Only Memory)—including PROMs, EPROMs, EEPROMs, flash memories, etc.—and RAM devices (RAM=Random Access Memory), e.g. DRAMs and SRAMs.
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address again later.
Since as many memory cells as possible are to be accommodated in a RAM device, one has been trying to realize them as simple as possible.
In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g. of few, for instance 6, transistors, and in the case of DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitive element (e.g. a trench capacitor) with the capacitance of which one bit can be stored as charge.
This charge, however, remains for a short time only. Therefore, a so-called “refresh” must be performed regularly, e.g., approximately every 64 ms.
In contrast to that, no “refresh” has to be performed in the case of SRAMs, i.e., the data stored in the memory cells remains stored as long as an appropriate supply voltage is fed to a respective SRAM.
In the case of non-volatile memory devices (NVMs), e.g. EPROMs, EEPROMs, flash memories, OTPs, etc., however, the stored data remains stored even when the supply voltage is switched off.
The memory cells provided in the above-mentioned memory devices are each adapted to be connected to corresponding bit lines so as to transmit a data value to be read out from a memory cell or a data value to be written into a memory cell.
On reading out a memory cell, an access transistor connected with a memory cell is first of all connected through by the activation or selection, respectively, of a word line, and the charge state stored in the memory cell is applied to the bit line. Later, the weak signal coming from the memory cell is amplified by a sense amplifier/evaluated by an evaluator circuit, respectively.
In the sense amplifier/evaluator circuit, the read current (Icell) resulting from the reading of a memory cell e.g. may be compared with a reference current (Iref), e.g. by use of respective current mirror devices.
The current mirror devices, e.g., might be connected to a supply voltage (Usupply), and to ground (VSS, e.g., 0V).
Further, the output of the current mirror devices might be connected to respective inverters.
If the read current (Icell) is bigger than the reference current (Iref), a voltage (Uver) at the output of the current mirror devices, i.e., the input of the inverters, is driven to the value of the above supply voltage (Usupply). Hence, e.g., a “logic 1” is output at the output of the inverters.
If, however, the read current (Icell) is smaller than the reference current (Iref), the voltage (Uver) at the output of the current mirror devices, i.e., the input of the inverters, is driven to ground, e.g., 0V. Hence, e.g., a “logic 0” is output at the output of the inverters.
Prior to the reading out of the memory cell, the corresponding bit line is precharged to a predetermined voltage (Uref), e.g. by a so-called precharge circuit that is connected with the corresponding bit line.
This—due to the parasitic capacitances of the bit line—takes a certain time t1 (“bit line charge time”).
During the bit line charge time t1, the voltage (Uver) at the output of the current mirror devices—as becomes clear from the explanations above—either has the value of the supply voltage (Usupply), or has a value of 0V (ground).
When reading out the memory cell, the voltage (Uver) at the output of the current mirror devices—as also becomes clear from the explanations above, and depending on the result of the above comparison between the read current (Icell) and the reference current (Iref)—might change e.g. from the value of the supply voltage (Usupply) to ground, e.g., 0V, or vice versa, i.e., from ground, to the value of the supply voltage (Usupply).
The state of the inverters e.g. might change when the voltage (Uver) at the output of the current mirror devices reaches 0.5*Usupply. Alternatively, for safety reasons; measures might be taken that ensure that the state of the inverters does not change before the voltage (Uver) at the output of the current mirror devices reaches 0.25*Usupply or 0.75*Usupply, respectively.
To charge the input of the inverters to 0.25*Usupply or 0.75*Usupply, respectively—due to respective parasitic capacitances—again takes a certain time t2 (“evaluation time”).
Further, the above inverters lead to a respective additional delay τgate delay of the output signal (“gate delay time”).
Hence, in total, the reading out of a memory cell might take a considerably long amount of time t1+t2+τgate delay.
For these or other reasons, there is a need for the present invention.